The present invention generally relates to a method of creating CMOS. More particularly, the present invention relates to a hybrid stacked nanowire featuring III-V nanowires and Ge.
High mobility III-V and Germanium (Ge) are attractive for 5 nm CMOS in a gate all around structures. For integration of III-V on Silicon (Si) substrate, growth on Si surfaces have shown promise. Growth of Ge can be slow and difficult.
As can be seen, there is a need for a hybrid orientation stacked nanowire featuring III-V nanowires and Ge.